Committee

Michaela Blott, Senior Fellow, AMD, Ireland

Michaela Blott has over 25 years of leading edge computer architecture and advanced FPGA and board design, in research institutions (ETH Zurich and Bell Labs) and development organizations.

She is heavily involved with the international research community, serving as the technical co-chair of FPL’2018, workshop organizer (H2RC) since 5 years, industry advisor on numerous EU projects, and member of numerous technical program committees (FPL, ISFPGA, DATE, etc.)

Boris Grot, Professor, School of Informatics, University of Edinburgh

Boris Grot is a Professor in the School of Informatics at the University of Edinburgh, where he leads the EASE Lab.

His research interests include server hardware and software stacks, networking, and datacenter-scale computing.

Boris is a member of the MICRO Hall of Fame and a recipient of multiple awards for his research. Boris was the Program Chair for MICRO 2022 and the General Chair for HPCA 2024.

Timothy Jones, Professor of Computer Architecture and Compilation, University of Cambridge

Timothy M. Jones is Professor of Computer Architecture and Compilation at the University of Cambridge Department of Computer Science and Technology and Director of the Computer Architecture Research Centre, as well as Fellow at Gonville and Caius college.

His research focuses on extracting many different forms of parallelism from applications to increase performance and address energy-efficiency and reliability challenges within compilers, binary translators and microarchitectures.

Paul Kelly, Professor of Software Technology, Imperial College London

Paul Kelly leads the Software Performance Optimisation group at Imperial College London.

His research focus is domain-specific program optimisation, leading to close engagement with colleagues in computational science, robotics and computer vision.

Sam Ainsworth, Visitor, School of Informatics, University of Edinburgh

Sam Ainsworth is a research consultant working in industry, and a Visitor at the University of Edinburgh.

His research looks at runtime, systems and hardware security, along with architectural and compiler techniques for data prefetching in software and hardware, and efficient techniques for hardware error detection and correction.

He received the Best Paper Award at MICRO 2023, the Distinguished Paper Award at ASPLOS 2023, and has had two papers receive IEEE Micro Top Picks.

He is regularly on the program committees of all of the top international conferences in computer architecture. Sam received a PhD in Computer Science from the University of Cambridge in 2018.

Matthew Leung, Research Director in Computer Architecture, Huawei Technologies Co. Ltd

Mr. Matthew Leung’s main duties lie in the development of next generation processor technologies. His expertise and experience is in the fields of VLSI design for advanced communication chipsets, microprocessors and artificial intelligence.

Mr. Leung received his BSc and MSc degrees of Electrical Engineering at the University of Michigan and Stanford University respectively. Before joining Huawei, he worked at Marvell Semiconductor, ASTRI, Sun Microsystems, Apple Computer, etc.

Satnam Singh, Fellow, Groq, United States of America

Satnam Singh is a Fellow at Groq where he works on the design and formal verification of chips for accelerating machine learning algorithms and compilers for machine learning chips.

Satnam has worked on a variety of projects at several companies including Google, Microsoft, Facebook and Xilinx on topics including configuring distributed systems, chip design, CAD tools, mobile app optimization and formal verification.

Before moving to industry, he was a lecturer at the University of Glasgow working on applying functional programming for FPGA designs.